ASU Spring Semester 2018 Week 3

This week in EEE 333 the focus has shifted to learning Verilog. Lab 2 was introduced and I’ve got a couple of weeks to put it together. For Lab 2 we’re building an ALU using Verilog in ModelSim and Quartus Prime to code our prototype boards. In addition, homework 2 required us to put together a module that would configure the hex displays on my prototype board to show either letters or numbers. Once I got the hand of it, it wasn’t too bad and by the end of the assignment I had my board saying “Hello World”. Very exciting. If that all wasn’t enough, I’ve got another quiz Friday night.

For EEE 335 Analog and Digital Circuits, the discussions has moved into dynamic operations, transistor sizing, and power dissipation. There have been some homework problems from the end of chapter and the second lab assignment on CMOS inverters will be due in a week or so. I was able to wrap up the lectures yesterday and plan to spend some time over the weekend and first part of next week to work through the lab in preparation for a quiz coming up in a week.

Below is a basic CMOS inverter schematic that I put together in Cadence. Looking forward to studying this a bit more to see how the various parameters impact its performance:


For the next two weeks, EEE350 Random Signal Analysis has eight different lecture topics. I’m starting to see how this class can be useful, but struggling a bit trying to figure out what the questions are asking. I think working through some additional problems will help with that.

The lecture topics included:

  • Sequential Experiments
  • Conditioning and Independence
  • Counting
  • Probabilities with Cards
  • Reliability Problems
  • Binomial Probabilities
  • Discrete Random Variables
  • Example of Discrete Probability
  • Expectation
  • Variance

Definitely a lot of material to sort through and get comfortable with.


ASU Spring Semester 2018 Week 2

This week has been busy! I think I’m still a little bit ahead which is good. I have a few labs coming up that look like they will be much more complicated so hopefully that cushion will be good.

In EEE 333 Hardware Design Language and Program Logic this week’s lectures covered quite a bit between CMOS and Verilog:

  • CMOS
    • Background CMOS Technology and IC Design
    • The MOSFET
    • Inverters and Gates
    • Operation and Modeling of MOSFETs
  • Verilog
    • Intro to Verilog
    • Boolean Expressions based Behavioral Models
    • Procedural Algorithms
    • Modelsim

Homework 1 had us rework an intro lab in Quartus Prime. No Verilog was required for that exercise and it was pretty straight forward. In addition to Homework 1, we had our first quiz covering the first three lectures. 12 questions, not too bad. Closed book, closed notes.

EEE 335 – Analog and Digital Circuits had us close up Unit 1 on MOS Transistor Structure and Operation. Homework 1 was due today, but I wrapped that up late last week. In addition, Lab 1 introducing the Cadence software is due Monday. I was able to get that done and submitted. No simulation, just recreating two schematics for a CMOS inverter and NAND gate. I’m sure future labs will be much more complicated.

EEE 350 – Random Signal Analysis has us closing up the first set of lectures and Homework 1 is due this weekend. Still not sure what I think of Random Signal Analysis. For the most part it’s been probability and set theory. I’m hoping that I can get the hang of that stuff. On its surface doesn’t seem that difficult and hopefully with a bit more practice I’ll get more comfortable.


ASU Spring Semester 2018 Week 1

This week has been a good week. Feels like the calm before the storm… Its been pretty light on homework, but lots of reading and lectures to watch as the foundation is laid out for future work.

EEE 333 – Hardware Design Language and Programmable Logic week 1 lectures gave an introduction to the course and walked us through setting up our lab environment on our works stations. This one has some interesting software that is used to program our development board. The course uses Modelsim and Quartus Prime to develop code for the various instructions and program the board. We’re using a Terasic DE0-CV board which uses an Altera Cyclone V FPGA device. It’s got some switches, buttons, LEDS, 7 segment displays… all sorts of things to work with.

Homework #1 was had us follow along and recreate an example circuit that uses eight of the switches, a button and the LEDs. A MUX was dropped onto the schematic wired up and the device programmed. The switches can be set and the button controls if the first four are used or the next four and depending on how the switches are set will light up the LEDS accordingly. So far so good and it is always a good feeling when the assignment works as specified.

Lab 0 required us to show that we either had ordered our dev board or had it and that the software is installed. Short of taking a bit of time to download everything and install the software, pretty straight forward.

I got started on Lab 1 which had us do some more work in Quartus laying out schematics. This time the requirements were to use constants that held the ASCII value of the first two letters of our last name and if button 1 was pushed show the first letter on the LEDS and then if the second button was pushed show the second letter. It wasn’t too bad to do other than I forgot that the buttons went off when pressed so I had my MUXs inputs switched. That was pretty easy to fix. Also initially I missed setting the name of the entity when the project was created so I had to redo that and add back in my schematic. I thought this lab was going to take a lot more time, but only took me about an hour. I am sure things will get much more complicated for the remaining four labs.

EEE 335 – Analog and Digital Circuits has been a very nice review of MOSFETs. The professor has worked through a lot of examples to review EEE334’s MOSFET lectures to really make sure we’ve got these down. I’ve really enjoyed the lectures and feel a lot more comfortable now with them. So far he’s only got one set of lectures posted and I worked ahead and got the homework problems already done. I plan to start in on the first lab assignment.

For the labs, we’re to use ASU’s EECAD servers. These are Linux servers so we’re using¬† VPN, SSH and then VNC to connect and run a software called Cadence. A little bit complicated, but works. I’ve never worked with the Cadence software before, but looks like it is used by various companies so will be good to get familiar with. Hopefully the connection to the servers works well. The professor had the online student runs through a stress test to make sure we were able to connect well before the drop date. I wish we could install the software on our own workstations, but the only option is through this VNC connection.¬†Doesn’t appear to be a hardware component for the labs.

EEE 350 – Random Signal Analysis, nothing is due this weekend, but there were seven videos to watch from Chapter one covering set theory, conditional probability, Bayes rule, and then some example problems. There are only three homework problems to work through so I knocked those out yesterday. Hopefully I can keep working ahead on this one. So far though seems to be more of a probability class than electrical engineering.

ASU Spring Semester 2018 Week 0

Nothing like waking up in the morning to three classes starting up. Officially ASU’s Spring 2018 semester starts up 1/8/2018, but the blackboard course shells were open this morning. I’m starting up on the Area Pathway Courses this semester and have the last of my required EEE courses to wrap up this semester. Students need four out six, but the other two pathway courses can be used for technical electives I’m told. In addition, will need to complete enough technical electives and then the two semester senior design project, but that comes next year.

The six pathways are:

  • Communication Signal Processing and Controls
  • Computer Engineering
  • Electronic Circuits
  • Electromagnetics
  • Solid State Electronics
  • Power Systems

I’m starting off with EEE 333 Hardware Design Languages and Program Logic in the Computer Engineer pathway and Analog and Digital Circuits in the Electronic Circuits pathway. In addition, I am trying my luck at EEE 350 Random Signal Analysis after having to withdraw from it last Fall. I’m not sure what the other two area pathway courses I’ll take will be but ASU’s EE Department, but am leaning towards Power Systems and just not sure what I’ll take for my fourth. I have a few more weeks until the Fall 2018 schedule becomes available to decide.

This morning, I’ve been going through the course schedule and syllabus. As usual, I keyed in all the assignments and due dates into Asana so I can plan out how I’m going to tackle this new mountain of work over the next 15 weeks.

I’m starting to see the light at the end of the tunnel though. Twelve courses remain for me to complete and if I can knock out three per semester I’ll be done in Fall 2019. It could be possible to finish up a little bit sooner if I were to take summer school, but with the accelerated pace, just not sure that really gets me much. I’m hoping I’ll be able to line up a paid summer internship for this summer and next summer to get some valuable experience.

In addition, next summer I think I will take the Fundamentals of Engineering exam so that will take up some of my time to prepare for that. All sorts of things to think about and prepare for.

Not much else to report today, but time to get started. Every problem solved gets me closer to the finish line!



ASU Fall Semester 2017 Complete

Another semester is done! Down to twelve classes left and excited to be on break. It was tough to keep focused towards the end there with these fifteen week classes. I’d gotten so used to only have to keep focused for 7.5 weeks, but having more time to work through the material was much better. I think the shift to 15 week courses is good.

EEE 241 Fundamentals of Electromagnetics I showed a bit of improvement from the second midterm to the final exam, but wasn’t able to pull off a B unfortunately and walked away with a C. I was six points shy and no curve short of the adjusted grading scale. I think the exam was fair though. It took me a little bit to figure this class out but I have passed it. I definitely don’t have it mastered by any means, but hopefully I’ll have a bit more practicing in my remaining courses. Not sure what more to say about it, it is by the hardest class that I’ve encountered. Perhaps if I had taken it right after MAT 267 and PHY 131 I would have done a bit better? Just not sure.

EEE 334 Circuits II’s final was graded much quicker than I was anticipating and the course grades posted this morning. Despite all the challenges in this course, I was able to get in A! I’m pretty proud of this score. I really enjoyed the labs and the topics covered in Circuits II once I got back into the swing of things. I messed up the logic circuit somehow and need to go back through and see what I did there. It was late when I took the exam and I think I swapped the pull up and pull down transistor networks accidently. Hopefully I’ll see a bit more of those in EEE335 next semester.

Next semester I’ll be taking two of four pathway courses with EEE 333 Hardware Design Language and Program Logic, EEE 335 Analog and Digital Circuits and then EEE 350 Random Signal Analysis is one of the upper division EEE required courses needed. Looks like I will be helping out for EEE120 as well so that will interesting. Rumor has it a few of the labs have been updated and am looking forward to helping out in there again.

That’s all for now. I’ll be back next year once Spring 2018 gets underway.

ASU Fall Semester 2017 Week 15

I’ve been having the worst week keeping focused on school without any new assignments or lectures to work on. I keep finding myself distracted looking at various Raspberry Pi, Arduino, or programming projects I want to mess with over the winter break when I should be studying and preparing for final exams.

I do better in the mornings at least and have been rewatching videos, reworking problems and examples and rereading the text book for EEE241. I keep hoping a light will finally turn on in my head, but so far can’t say it has yet. Short of praying to Lords Faraday, Maxwell, Ampere and Gauss not sure what more can be done and just hoping I can put slightly coherent ink strokes down on my paper in response to the three questions that will be asked. I just need 8 points out of 30 if my math is correct to pull off a C in EEE241 and that is all I want for Christmas.

EEE334 I’m in better shape there and even if I bomb the final, I still walk away with a C. I think I worked out that I can score a 70% on the final and still have an A. Hopefully all the necessary values will be given, the problems will be clear and the clock won’t be too bad. The professor has been MIA for a bit and hasn’t given much information at all short of its cumulative. I have been reviewing the past quizzes and homework assignments in there.

So next week, my plan is to take the EEE241 final on Tuesday night and then EEE334 Wednesday night and that will wrap up the Fall 2017 semester. With any luck grades will be posted by the end of the weekend and then it’s relax and recharge a bit. I’ll put together a final thoughts post once grades are posted.

ASU Fall Semester 2017 Week 14

EEE 241 had only two problems this week for the final homework set. Lectures this week included:

  • Transverse Electromagnetic Waves
  • Polarization of Plane Waves
  • Plane Waves in Lossy Media
  • Propagation in Ionized Gases
  • Group Velocity
  • The Poynting Vector

This wraps up the video lectures for EEE 241. Next week planning to revisit a lot of the lectures and examples to see if I can find the missing pieces.

EEE 334 was a bit busy this week with Quiz #6 and working on the last homework assignment. The homework assignment focused on Chapter 14 on Digital CMOS.

At this point, all assignments have been turned in short of the final exams. Hopefully over the next few days the graders will get scores posted. Next week, my focus will be on reviewing for the final exams. Not much else to say at this point, but definitely will be glad to get these two courses behind me.