ASU Spring Semester 2018 Week 7

Two midterms in one week with a lab and couple of homework assignments. Toss in your oldest son becoming a Boy Scout, plus dad and step mom coming into town, oh and then my wife gone for the weekend to a knitting convention and me left with the three kids…

For some reason, I missed my Friday update.

Last Monday I had my EEE 335 Random Signal Analysis and I did pretty well. I missed one. Each question was worth 8 points, 15 questions so 120 points possible. The exam is only graded out of 100 points so right now I’ve got 12 extra credit points. Not bad. After Monday, I honestly ignored EEE 350 all week.

Thursday, I took my EEE 335 midterm and feel like I got my butt kicked. I should have started sooner and just wasn’t as prepared as I should have been. As of Sunday, no results have been posted so hopefully it isn’t as bad as I fear. Guess we will see what happens.

In addition to the midterm. Lab 3 on various CMOS Circuits took up a bit of time. It was initially due on Monday 2/26, but got pushed back a week. Luckily I had just finished up the lab, when I saw the announcement.

EEE 335 Digital and Analog Circuits is now moving into Analog circuits. I just started watching the various lectures and so far it’s been a nice review of some of the EEE 334 topics. I’m sure it will get much more complicated very soon.

EEE 333 – Hardware Programming Languages had three lectures last week covering Finite State Machines in Verilog and Test Benches. Pretty interesting topics and picked up a few neat tricks in the test bench lectures. The homework for the week had us working with counters, different latches and flip flops. This class is definitely a lot of work and students can’t wait until the night before to get started on assignments.

Lastly, I registered for classes on Friday for the Fall Semester. I had initially been thinking of taking the summer off to find an internship, but I really want to be done with school. I have decided to take EEE 352 – Properties of Electronic Materials this summer. In the Fall –

  • EEE 360 Energy Systems and Power Electronics
  • EEE 436 Fundamentals of Solid State Devices
  • EEE 463 Electrical Power Plants
  • EEE 488 Senior Design Laboratory I

It’s going to be even busier, but provided I can make it through the summer and fall, and the four classes in the Spring I’ll be done in May 2019! I’m looking forward to the Senior Design Lab course, but first things first. I’ve got to do better in EEE 335 and pass the courses in front of me.

ASU Spring Semester 2018 Week 6

The first exam results from EEE 333 Hardware Design Language and Program Logic posted early this past week and I was able to pull off a 91%. I made some silly mistakes which cost me a few points on a couple of questions rushing through trying to finish. There weren’t any big surprises, just need to pay better attention to the details moving forward. The average score was a B, so I was above average on it regardless.

I was able to submit my lab report for the arithmetic logic unit earlier in the week which is due tomorrow. I started on it weeks ago and then we had another homework assignment to build a few of the components I needed for it so figured to just get it done and behind me.

In addition to that, this week’s homework assignment has been to build a finite state machine that will detect a bit string sequence of 1101. For this FSM, the assignment specified to use a Moore machine over Mealy. It is definitely a lot easier putting those together in Verilog where you can use case statements than it was in EEE 120 having to sort out state transition tables! This was a fun assignment.

In EEE 335 Analog and Digital Circuits, two lectures covered Memory Chip Organization and the Static Memory Cell. There were only six homework assignment questions in addition to the second quiz due today. Lab 3 will be due at the end of the month so I’ll be starting to work on that.

Next Thursday we have our first big exam which is 20% of the grade for the class covering everything we’ve done up until now. It will be closed book and notes, but we get a two page sheet of notes to bring in with us. I have a lot of work to do over the coming days to prepare for it.

Lastly in EEE 350 Random Signal Analysis, my focus has been on reviewing example problems, reading and studying for the big midterm on Monday. I have had homework set 3 done that is due Sunday for a couple of days now, just need to submit it. The midterm looks to be centered around Chapters 1-4 and Chapter 7 in the 3rd edition. 15 questions, 8 points a piece with 20 bonus points available if one can score over 100 points. I hope my preparations will be enough. It’s multiple choice so you’re either right or wrong. Rumor has it that these exams are really tricky as well. I hope I can do okay.

There really isn’t enough going on, but next week the fall schedule for 2018 comes out and I will register on Friday 2/23. After this semester provided I pass everything, I will have 2 pathway courses, 5 tech electives and the two classes for the Senior Design Project. I am pretty sure I will take EEE 360 Energy Systems and Power Electronics for on of the remaining pathway courses and I am really not sure which one I will take for the fourth. It comes down to EEE 304 Signals and Systems II, EEE 341 Engineering Electromagnetics and EEE 352 Properties of Electronic Materials. I did do great in EEE 241 so not too excited to go back into that world of electromagnetics. EEE 203 Signals and Systems I wasn’t my favorite course and EEE 304 I’ve heard is challenging and then EEE 352 just not sure there. Not sure which elective I’ll take, some are only offered once every few years so will just have to see. So many big decisions as I start to head towards the finish line…

ASU Spring Semester 2018 Week 5

This morning I had my first midterm in EEE 333. It doesn’t close until Saturday at 6pm so I’ll save my thoughts on it for next week. Hopefully will know how I did, but man, felt like sprinting a marathon!

In EEE 333 – Hardware Programming Languages this week surprisingly centered around preparing for the first midterm. The professor provided a very good pretest as a homework assignment to help us prepare and focus. In addition to that homework assignment, we have an assignment to write up a couple of different modules that will be useful for our ALU Lab 2 that is coming due next weekend. I was able to get that knocked out well in advance of its due date which is Monday and plan to over the next few days, wrap up the Lab. I am close, but still need to put in my two’s complement, test a bit more code, and then get it uploaded to my FPGA, documented, and then submitted.

In addition to all those assignments and a midterm, the lectures this week turned their attention to Latches, Flip Flops and Counters. All very useful things. So far, no assignments with these yet, but I’m sure we’ll be working with them in ModelSim in the next few weeks quite a bit.

I am enjoying this class despite all the work. I like working with the various software applications we have. I still make silly mistakes sometimes on my Boolean simplifications when working them on paper, like loosing a NOT along the way, but hopefully I’ll grow out of that soon. I am definitely checking all my work with the Logisim application from EEE120 and that is really helpful to make sure the minimum SOP or POS forms of equations are found.

EEE 335 – Analog and Digital Circuits continues to be really interesting. It’s lectures and homework this past week started to look at

  • Memory Circuits
  • Latches and Flip Flops
  • SR and D Flip Flops

All topics that we’re looking at EEE 333 as well so definitely helpful having that overlap between the two classes although EEE 335 is more focused on the various gates and transistors needed, where EEE 333 is looking at the software Verilog implementations. This week’s homework assignment for EEE 335 had us working on 6 problems across chapters 15 and 16.

I haven’t started Lab 3 yet for EEE 335, but will be starting to chip away at that starting soon. Still have a bit of time, but starting early is prudent as something always seems to take longer to figure out than one anticipates.

EEE 350 – Random Signal Analysis – this class is the odd ball. I have my first midterm on 2/19 and started my review of the material that will be on the test. A sample midterm posted so I’ll be going through that this weekend. It’s hard to describe, but this class is just strange to me. Sometimes I can figure out what is going on with a homework question and other times its very odd. The notation the various axioms and formulas make things sometimes seem harder than the calculations really are.

For my review I’m going through all of the examples in the book and putting together my formula sheet for the exam and am hoping I’ll be prepared and can make sense of what the questions are asking. It’s very little EE stuff, lots of math and probability.

The lectures I watched this week included topics on:

  • Conditioning PMFs on Events
  • Continuous RV, PDFs Mean and Variance
  • Cumulative Distribution Functions
  • Examples involving PDFs
  • Mixed Distributions
  • Examples of Continuous Distributions

No rest for me following my EEE 333 midterm. Off to knock out another couple of problems!


ASU Spring Semester 2018 Week 4

February is here! In EEE 350 Random Signal Analysis I wrapped up the second homework set and got that submitted well before Sunday’s deadline. I’ve been trying to keep ahead, but this stuff is definitely a tricky. I ordered a Schaum’s guide in the hopes that seeing a slight different perspective will help this stuff stick. February 19th, I’ve got my first midterm in 350 so preparation will be picking up.

EEE 335 Analog and Digital Circuits has been really interesting. Lecture topics have included:

  • Dynamic Operation of CMOS Inverters
  • Transistor Sizing
  • Power Dissipation

There were a couple of book problems for Homework #3, plus a quiz, AND a lab due Monday. I believe I’ve got Lab #2 wrapped up and ready to submit Monday, just need to double check and make sure I’ve got everything accounted for. The quiz wasn’t bad at all, especially give that we had two attempts and the answers were provided after the first. First time, I’ve had a quiz like that, seemed like a free 10 points. I need to do a better job catching up the various recitation recordings that the professor has been uploading. The 1st midterm for 335 is also the week of 2/19.

EEE 333 Hardware Design Language and Program Logic has been focused on Boolean Logic and Number Systems, Karnaugh Maps, Multiplexers, Tristate Buffers and Demultiplexers. I’ve been continuing to chip away at the ALU Lab 2. The professor assigned a pretty good size homework set that had me working a lot of Boolean Simplifications and Karnaugh Maps. Next week is the first exam. The professor put together a pretest homework assignment due Monday that will hopefully put me in pretty good shape, combined with reviewing the various quizzes and lectures and homework assignments.